Programmer_ATM328p/ASM_Source/main.s

;Incs and Defs---------------------------------------------------------

.include "atm328p.inc"
.include "global.inc"

;**********************************************************************
;**********************************************************************
;Hauptprogramm

.global main
main:

;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;Phase_1: Initialization
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

	ldi		main_r, lo8(RAMEND)					;Stackpointer
	out		SPL, main_r
	ldi		main_r, hi8(RAMEND)
	out		SPH, main_r
	
	ldi		true, 0xFF							;Default-Register
	ldi		false, 0x00

	call	timer1_reset						;reset Timer1
	ldi		timer1_r, 1<<CS12					;Prescaler x256 (1Hz)
	sts		TCCR1B, timer1_r					
	ldi		timer1_r, 0x05						;Timer1-Delay (5s)	
	sts		timer1_MAX, timer1_r
	ldi		timer1_r, 1<<TOIE1					;Timer1-OVF enable
	sts		TIMSK1, timer1_r

    sei											;Interrupts aktivieren

	ldi		main_r, (1<<PC0)|(1<<PC1)|(1<<PC2)|(1<<PC3)|(1<<PC4)	
	out		DDRC, main_r						;init I/O
	out 	PORTC, false						

	call	timer2_init							;init Timer2 auf 10Hz
	ldi		timer2_r, 0x06
	sts 	timer2_MAX, timer2_r
	ldi		timer2_r, 1<<PC0					;toggle PC0
	sts 	timer2_var, timer2_r				
	ldi		timer2_r, 1<<TOIE2					;Timer2-OVF enable
	sts		TIMSK2, timer2_r

	call	usart_init							;USART

	lds		timer1_r, timer1_bool				;Timer1_Delay (5s)
	cpse	timer1_r, true
	rjmp	.-8
	sts		TIMSK1, false						;Timer1-OVF disable
				
	sts		TIMSK2, false						;Timer2-OVF disable

	sbi		PORTC, PC0							;Phase_1 complete

;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;Phase2: Prepare uC for Programming
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

	call	timer1_reset						;reset Timer1
	ldi		timer1_r, 1<<CS12					;Prescaler x256 (1Hz)
	sts		TCCR1B, timer1_r					
	ldi		timer1_r, 0x01						;Timer1-Delay (1s)	
	sts		timer1_MAX, timer1_r
	ldi		timer1_r, 1<<TOIE1					;Timer1-OVF enable
	sts		TIMSK1, timer1_r

	call	timer2_init							;init Timer2 auf 10Hz
	ldi		timer2_r, 0x06
	sts 	timer2_MAX, timer2_r
	ldi		timer2_r, 1<<PC1					;toggle PC1
	sts 	timer2_var, timer2_r				
	ldi		timer2_r, 1<<TOIE2					;Timer2-OVF enable
	sts		TIMSK2, timer2_r

;

	lds		timer1_r, timer1_bool				;Timer1 Delay (1s)
	cpse	timer1_r, true
	rjmp	.-8
	sts		TIMSK1, false						;Timer1-OVF disable

	sts		TIMSK2, false						;Timer2-OVF disable

	sbi		PORTC, PC1							;Phase_2 complete

;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;Phase_3: Connection to Interface and Page send
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

	call	timer1_reset						;reset Timer1
	ldi		timer1_r, 1<<CS12					;Prescaler x256 (1Hz)
	sts		TCCR1B, timer1_r					
	ldi		timer1_r, 0x01						;Timer1-Delay (1s)	
	sts		timer1_MAX, timer1_r
	ldi		timer1_r, 1<<TOIE1					;Timer1-OVF enable
	sts		TIMSK1, timer1_r

	call	timer2_init							;init Timer2 auf 10Hz
	ldi		timer2_r, 0x06
	sts 	timer2_MAX, timer2_r
	ldi		timer2_r, 1<<PC2					;toggle PC2
	sts 	timer2_var, timer2_r				
	ldi		timer2_r, 1<<TOIE2					;Timer2-OVF enable
	sts		TIMSK2, timer2_r

;Recieve Request-------------------------------------------------------

	sts		pagemode, false						;disable Pagemode
	ldi		X_l, lo8(req_ptr)					;Pointer 'REQ'
	ldi		X_h, hi8(req_ptr)
	sts		req_complete, false

	lds		usart_r, UCSR0B						;enable RX, RXCI
	sbr		usart_r, (1<<RXEN0)|(1<<RXCIE0)
	sts		UCSR0B, usart_r

	lds		usart_r, req_complete				;wait for Request
	cpse	usart_r, true
	rjmp	.-8

	lds		usart_r, UCSR0B						;disable RX,UDRIE,RXCI
	cbr		usart_r, (1<<RXEN0)|(1<<UDRIE0)|(1<<RXCIE0)
	sts		UCSR0B, usart_r
	sts		UDR0, false							;clear UDR

;Send Acknoledgement---------------------------------------------------

	ldi		X_l, lo8(ack_ptr)					;Pointer 'ACK'
	ldi		X_h, hi8(ack_ptr)
	sts		ack_complete, false	

	lds		usart_r, UCSR0B						;enable TX, UDREI
	sbr		usart_r, (1<<TXEN0)|(1<<UDRIE0)
	sts		UCSR0B, usart_r

	lds		usart_r, ack_complete				;wait for ACK send
	cpse	usart_r, true
	rjmp	.-8

	lds		usart_r, UCSR0B						;disable TX,UDREI,TXCI
	cbr		usart_r, (1<<TXEN0)|(1<<UDRIE0)|(1<<TXCIE0)
	sts		UCSR0B, usart_r
	sts		UDR0, false							;clear UDR

;Recieve Page----------------------------------------------------------

	ldi		X_l, lo8(page_ptr)					;Page-Pointer
	ldi		X_h, hi8(page_ptr)
	sts		pagemode, true						;enable Pagemode

	lds		usart_r, UCSR0B						;enable RX, RXCI
	sbr		usart_r, (1<<RXEN0)|(1<<RXCIE0)
	sts		UCSR0B, usart_r
	
	lds		usart_r, pagemode					;wait for Page received
	cpse	usart_r, false
	rjmp	.-8

	lds		usart_r, UCSR0B						;disable RX,UDRIE,RXCI
	cbr		usart_r, (1<<RXEN0)|(1<<UDRIE0)|(1<<RXCIE0)
	sts		UCSR0B, usart_r
	sts		UDR0, false							;clear UDR	

	lds		timer1_r, timer1_bool				;Timer1 Delay (1s)
	cpse	timer1_r, true
	rjmp	.-8
	sts		TIMSK1, false						;Timer1-OVF disable

	sts		TIMSK2, false						;Timer2-OVF disable

	sbi		PORTC, PC2							;Phase_3 complete

;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;Phase_4: Write Page on uC
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

	call	timer1_reset						;reset Timer1
	ldi		timer1_r, 1<<CS12					;Prescaler x256 (1Hz)
	sts		TCCR1B, timer1_r					
	ldi		timer1_r, 0x01						;Timer1-Delay (1s)	
	sts		timer1_MAX, timer1_r
	ldi		timer1_r, 1<<TOIE1					;Timer1-OVF enable
	sts		TIMSK1, timer1_r

	call	timer2_init							;init Timer2 auf 10Hz
	ldi		timer2_r, 0x06
	sts 	timer2_MAX, timer2_r
	ldi		timer2_r, 1<<PC3					;toggle PC3
	sts 	timer2_var, timer2_r				
	ldi		timer2_r, 1<<TOIE2					;Timer2-OVF enable
	sts		TIMSK2, timer2_r

;

	lds		timer1_r, timer1_bool				;Timer1 Delay (1s)
	cpse	timer1_r, true
	rjmp	.-8
	sts		TIMSK1, false						;Timer1-OVF disable

	sts		TIMSK2, false						;Timer2-OVF disable

	sbi		PORTC, PC3							;Phase_4 complete

;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;Phase_5: Read Flash of uC and control Checksum
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

	call	timer1_reset						;reset Timer1
	ldi		timer1_r, 1<<CS12					;Prescaler x256 (1Hz)
	sts		TCCR1B, timer1_r					
	ldi		timer1_r, 0x01						;Timer1-Delay (1s)	
	sts		timer1_MAX, timer1_r
	ldi		timer1_r, 1<<TOIE1					;Timer1-OVF enable
	sts		TIMSK1, timer1_r

	call	timer2_init							;init Timer2 auf 10Hz
	ldi		timer2_r, 0x06
	sts 	timer2_MAX, timer2_r
	ldi		timer2_r, 1<<PC4					;toggle PC4
	sts 	timer2_var, timer2_r				
	ldi		timer2_r, 1<<TOIE2					;Timer2-OVF enable
	sts		TIMSK2, timer2_r

;

	lds		timer1_r, timer1_bool				;Timer1 Delay (1s)
	cpse	timer1_r, true
	rjmp	.-8
	sts		TIMSK1, false						;Timer1-OVF disable

	sts		TIMSK2, false						;Timer2-OVF disable

	sbi		PORTC, PC4							;Phase_5 complete

;Programmende----------------------------------------------------------
	rjmp	.-2									;Endlosschleife
	cli											;