ASM-Source, USART

Source/ASM_Source/atm328p.inc

@@ -0,0 +1,622 @@
+;Internal I/O-Registers------------------------------------------------
+
+.equ	SREG,	0x3f    ;Intern
+.equ	SPL,	0x3d    ;Intern
+.equ	SPH,	0x3e    ;Intern
+.equ	SPMCSR, 0x37    ;Intern
+.equ	MCUCR,  0x35    ;Intern
+.equ	MCUSR,  0x34    ;Intern
+.equ	SMCR,   0x33    ;Intern
+.equ	ACSR,   0x30    ;Intern
+.equ	SPDR,   0x2e    ;Intern
+.equ	SPSR,   0x2d    ;Intern
+.equ	SPCR,   0x2c    ;Intern
+.equ	GPIOR2, 0x2b    ;Intern
+.equ	GPIOR1, 0x2a    ;Intern
+.equ	OCR0B,  0x28    ;Intern
+.equ	OCR0A,  0x27    ;Intern
+.equ	TCNT0,  0x26    ;Intern
+.equ	TCCR0B, 0x25    ;Intern
+.equ	TCCR0A, 0x24    ;Intern
+.equ	GTCCR,  0x23    ;Intern
+.equ	EEARH,  0x22    ;Intern
+.equ	EEARL,  0x21    ;Intern
+.equ	EEDR,   0x20    ;Intern
+.equ	EECR,   0x1f    ;Intern
+.equ	GPIOR0, 0x1e    ;Intern
+.equ	EIMSK,  0x1d    ;Intern
+.equ	EIFR,   0x1c    ;Intern
+.equ	PCIFR,  0x1b    ;Intern
+.equ	TIFR2,  0x17    ;Intern
+.equ	TIFR1,  0x16    ;Intern
+.equ	TIFR0,  0x15    ;Intern
+.equ	PORTD,  0x0b    ;Intern
+.equ	DDRD,   0x0a    ;Intern
+.equ	PIND,   0x09    ;Intern
+.equ	PORTC,  0x08    ;Intern
+.equ	DDRC,   0x07    ;Intern
+.equ	PINC,   0x06    ;Intern
+.equ	PORTB,  0x05    ;Intern
+.equ	DDRB,   0x04    ;Intern
+.equ	PINB,   0x03    ;Intern
+
+
+;External I/O-Registers------------------------------------------------
+
+.equ	UDR0,	0xc6	;Extern
+.equ	UBRR0L, 0xc4	;Extern
+.equ	UBRR0H, 0xc5	;Extern
+.equ	UCSR0C, 0xc2	;Extern
+.equ	UCSR0B, 0xc1	;Extern
+.equ	UCSR0A, 0xc0	;Extern
+.equ	TWAMR,	0xbd	;Extern
+.equ	TWCR,	0xbc	;Extern
+.equ	TWDR,	0xbb	;Extern
+.equ	TWAR,	0xba	;Extern
+.equ	TWSR,	0xb9	;Extern
+.equ	TWBR,	0xb8	;Extern
+.equ	ASSR,	0xb6	;Extern
+.equ	OCR2B,	0xb4	;Extern
+.equ	OCR2A,	0xb3	;Extern
+.equ	TCNT2,	0xb2	;Extern
+.equ	TCCR2B, 0xb1	;Extern
+.equ	TCCR2A, 0xb0	;Extern
+.equ	OCR1BL, 0x8a	;Extern
+.equ	OCR1BH, 0x8b	;Extern
+.equ	OCR1AL, 0x88	;Extern
+.equ	OCR1AH, 0x89	;Extern
+.equ	ICR1L,  0x86	;Extern
+.equ	ICR1H,  0x87	;Extern
+.equ	TCNT1L, 0x84	;Extern
+.equ	TCNT1H, 0x85	;Extern
+.equ	TCCR1C, 0x82	;Extern
+.equ	TCCR1B, 0x81	;Extern
+.equ	TCCR1A, 0x80	;Extern
+.equ	DIDR1,  0x7f	;Extern
+.equ	DIDR0,  0x7e	;Extern
+.equ	ADMUX,  0x7c	;Extern
+.equ	ADCSRB, 0x7b	;Extern
+.equ	ADCSRA, 0x7a	;Extern
+.equ	ADCH,   0x79	;Extern
+.equ	ADCL,   0x78	;Extern
+.equ	TIMSK2, 0x70	;Extern
+.equ	TIMSK1, 0x6f	;Extern
+.equ	TIMSK0, 0x6e	;Extern
+.equ	PCMSK1, 0x6c	;Extern
+.equ	PCMSK2, 0x6d	;Extern
+.equ	PCMSK0, 0x6b	;Extern
+.equ	EICRA,  0x69	;Extern
+.equ	PCICR,  0x68	;Extern
+.equ	OSCCAL, 0x66	;Extern
+.equ	PRR,	0x64	;Extern
+.equ	CLKPR,	0x61	;Extern
+.equ	WDTCSR, 0x60	;Extern
+
+
+;USART0-Interface------------------------------------------------------
+
+;UCSR0A
+.equ	MPCM0,	0	;Multi-processor Communication Mode
+.equ	U2X0,	1	;Double the USART transmission speed
+.equ	UPE0,	2	;Parity Error
+.equ	DOR0,	3	;Data overRun
+.equ	FE0,	4	;Framing Error
+.equ	UDRE0,	5	;USART Data Register Empty
+.equ	TXC0,	6	;USART Transmitt Complete
+.equ	RXC0,	7	;USART Receive Complete
+
+;UCSR0B
+.equ	TXB80,	0	;Transmit Data Bit 8
+.equ	RXB80,	1	;Receive Data Bit 8
+.equ	UCSZ02,	2	;Character Size
+.equ	TXEN0,	3	;Transmitter Enable
+.equ	RXEN0,	4	;Receiver Enable
+.equ	UDRIE0,	5	;USART Data register Empty Interrupt Enable
+.equ	TXCIE0,	6	;TX Complete Interrupt Enable
+.equ	RXCIE0,	7	;RX Complete Interrupt Enable
+
+;UCSR0C
+.equ	UCPOL0,	0	;Clock Polarity
+.equ	UCSZ00,	1	;Character Size
+.equ	UCSZ01,	2	;Character Size
+.equ	USBS0,	3	;Stop Bit Select
+.equ	UPM00,	4	;Parity Mode Bit 0
+.equ	UPM01,	5	;Parity Mode Bit 1
+.equ	UMSEL00,6	;USART Mode Select
+.equ	UMSEL01,7	;USART Mode Select
+
+
+;2Wire-Interface-------------------------------------------------------
+
+;TWCR
+.equ	TWIE,	0	;TWI Interrupt Enable
+.equ	TWEN,	2	;TWI Enable Bit
+.equ	TWWC,	3	;TWI Write Collition Flag
+.equ	TWSTO,	4	;TWI Stop Condition Bit
+.equ	TWSTA,	5	;TWI Start Condition Bit
+.equ	TWEA,	6	;TWI Enable Acknowledge Bit
+.equ	TWINT,	7	;TWI Interrupt Flag
+
+;TWSR
+.equ	TWPS0,	0	;TWI Prescaler
+.equ	TWPS1,	1	;TWI Prescaler
+.equ	TWS3,	3	;TWI Status
+.equ	TWS4,	4	;TWI Status
+.equ	TWS5,	5	;TWI Status
+.equ	TWS6,	6	;TWI Status
+.equ	TWS7,	7	;TWI Status
+
+;TWAR
+.equ	TWGCE,	0	;TWI General Call Recognition Enable Bit
+
+
+;Timer/Counter0-------------------------------------------------------
+
+;TIMSK0
+.equ	TOIE0,	0	;Overflow Interrupt Enable
+.equ	OCIE0A,	1	;Output Compare Match A Interrupt Enable
+.equ	OCIE0B,	2	;Output Compare Match B Interrupt Enable
+
+;TIFR0
+.equ	TOV0,	0	;Overflow Flag
+.equ	OCF0A,	1	;Output Compare Flag 0A
+.equ	OCF0B,	2	;Output Compare Flag 0B
+
+;TCCR0A
+.equ	WGM00,	0	;Waveform Generation Mode
+.equ	WGM01,	1	;Waveform Generation Mode
+.equ	COM0B0,	4	;Compare Output Mode, Fast PWm
+.equ	COM0B1,	5	;Compare Output Mode, Fast PWm
+.equ	COM0A0,	6	;Compare Output Mode, Phase Correct PWM Mode
+.equ	COM0A1,	7	;Compare Output Mode, Phase Correct PWM Mode
+
+;TCCR0B
+.equ	CS00,	0	;Clock Select
+.equ	CS01,	1	;Clock Select
+.equ	CS02,	2	;Clock Select
+.equ	WGM02,	3	;Waveform Generation Mode 
+.equ	FOC0B,	6	;Force Output Compare B
+.equ	FOC0A,	7	;Force Output Compare A
+
+
+;Timer/Counter1--------------------------------------------------------
+
+;TIMSK1
+.equ	TOIE1,	0	;Overflow Interrupt Enable
+.equ	OCIE1A,	1	;Output CompareA Match Interrupt Enable
+.equ	OCIE1B,	2	;Output CompareB Match Interrupt Enable
+.equ	ICIE1,	5	;Input Capture Interrupt Enable
+
+;TIFR1
+.equ	TOV1,	0	;Overflow Flag
+.equ	OCF1A,	1	;Output Compare Flag 1A
+.equ	OCF1B,	2	;Output Compare Flag 1B
+.equ	ICF1,	5	;Input Capture Flag 1
+
+;TCCR1A
+.equ	WGM10,	0	;Waveform Generation Mode
+.equ	WGM11,	1	;Waveform Generation Mode
+.equ	COM1B0,	4	;Compare Output Mode 1B, bit 0
+.equ	COM1B1,	5	;Compare Output Mode 1B, bit 1
+.equ	COM1A0,	6	;Comparet Ouput Mode 1A, bit 0
+.equ	COM1A1,	7	;Compare Output Mode 1A, bit 1
+
+;TCCR1B
+.equ	CS10,	0	;Prescaler source of Timer/Counter 1
+.equ	CS11,	1	;Prescaler source of Timer/Counter 1
+.equ	CS12,	2	;Prescaler source of Timer/Counter 1
+.equ	WGM12,	3	;Waveform Generation Mode
+.equ	WGM13,	4	;Waveform Generation Mode
+.equ	ICES1,	6	;Input Capture 1 Edge Select
+.equ	ICNC1,	7	;Input Capture 1 Noise Canceler
+
+;TCCR1C
+.equ	FOC1B,	6	;Force Output Compare A 
+.equ	FOC1A,	7	;Force Output Compare B
+
+;GTCCR
+.equ	PSRSYNC,0	;Prescaler Reset Timer/Counter1 and Timer/Counter0
+.equ	TSM,	7	;Timer/Counter Synchronization Mode
+
+
+;Timer/Counter2-------------------------------------------------------
+
+;TIMSK2
+.equ	TOIE2,	0	;Overflow Interrupt Enable
+.equ	OCIE2A,	1	;Output Compare Match A Interrupt Enable
+.equ	OCIE2B,	2	;Output Compare Match B Interrupt Enable
+
+;TIFR2
+.equ	TOV2,	0	;Overflow Flag
+.equ	OCF2A,	1	;Output Compare Flag 2A
+.equ	OCF2B,	2	;Output Compare Flag 2B
+
+;TCCR2A
+.equ	WGM20,	0	;Waveform Genration Mode
+.equ	WGM21,	1	;Waveform Genration Mode
+.equ	COM2B0,	4	;Compare Output Mode bit 0
+.equ	COM2B1,	5	;Compare Output Mode bit 1
+.equ	COM2A0,	6	;Compare Output Mode bit 1
+.equ	COM2A1,	7	;Compare Output Mode bit 1
+
+;TCCR2B
+.equ	CS20,	0	;Clock Select bit 0
+.equ	CS21,	1	;Clock Select bit 1
+.equ	CS22,	2	;Clock Select bit 2
+.equ	WGM22,	3	;Waveform Generation Mode
+.equ	FOC2B,	6	;Force Output Compare B
+.equ	FOC2A,	7	;Force Output Compare A
+
+;ASSR
+.equ	TCR2BUB,0	;Timer/Counter Control Register2 Update Busy
+.equ	TCR2AUB,1	;Timer/Counter Control Register2 Update Busy
+.equ	OCR2BUB,2	;Output Compare Register 2 Update Busy
+.equ	OCR2AUB,3	;Output Compare Register2 Update Busy
+.equ	TCN2UB,	4	;Timer/Counter2 Update Busy
+.equ	AS2,	5	;Asynchronous Timer/Counter2
+.equ	EXCLK,	6	;Enable External Clock Input
+
+;GTCCR
+.equ	PSRASY,	1	;Prescaler Reset Timer/Counter2
+
+;AD-Converter--------------------------------------------------------
+
+;ADMUX
+.equ	MUX0,	0	;Analog Channel and Gain Selection Bits
+.equ	MUX1,	1	;Analog Channel and Gain Selection Bits
+.equ	MUX2,	2	;Analog Channel and Gain Selection Bits
+.equ	MUX3,	3	;Analog Channel and Gain Selection Bits
+.equ	ADLAR,	5	;Left Adjust Result
+.equ	REFS0,	6	;Reference Selection Bit 0
+.equ	REFS1,	7	;Reference Selection Bit 1
+
+;ADCSRA
+.equ	ADPS0,	0	;ADC  Prescaler Select Bits
+.equ	ADPS1,	1	;ADC  Prescaler Select Bits
+.equ	ADPS2,	2	;ADC  Prescaler Select Bits
+.equ	ADIE,	3	;ADC Interrupt Enable
+.equ	ADIF,	4	;ADC Interrupt Flag
+.equ	ADATE,	5	;ADC  Auto Trigger Enable
+.equ	ADSC,	6	;ADC Start Conversion
+.equ	ADEN,	7	;ADC Enable
+
+;ADCSRB
+.equ	ADTS0,	0	;ADC Auto Trigger Source bit 0
+.equ	ADTS1,	1	;ADC Auto Trigger Source bit 1
+.equ	ADTS2,	2	;ADC Auto Trigger Source bit 2
+
+; DIDR0 - Digital Input Disable Register
+.equ	ADC0D,	0	 
+.equ	ADC1D,	1	 
+.equ	ADC2D,	2	 
+.equ	ADC3D,	3	 
+.equ	ADC4D,	4	 
+.equ	ADC5D,	5	 
+
+
+;Analog-Comparator----------------------------------------------------
+
+;ACSR
+.equ	ACIS0,	0	;Analog Comparator Interrupt Mode Select bit 0
+.equ	ACIS1,	1	;Analog Comparator Interrupt Mode Select bit 1
+.equ	ACIC,	2	;Analog Comparator Input Capture Enable
+.equ	ACIE,	3	;Analog Comparator Interrupt Enable
+.equ	ACI,	4	;Analog Comparator Interrupt Flag
+.equ	ACO,	5	;Analog Compare Output
+.equ	ACBG,	6	;Analog Comparator Bandgap Select
+.equ	ACD,	7	;Analog Comparator Disable
+
+;DIDR1
+.equ	AIN0D,	0	;AIN0 Digital Input Disable
+.equ	AIN1D,	1	;AIN1 Digital Input Disable
+
+
+;PORTB----------------------------------------------------------------
+
+.equ	PB0,	0	;Port B Data Register bit 0
+.equ	PB1,	1	;Port B Data Register bit 1
+.equ	PB2,	2	;Port B Data Register bit 2
+.equ	PB3,	3	;Port B Data Register bit 3
+.equ	PB4,	4	;Port B Data Register bit 4
+.equ	PB5,	5	;Port B Data Register bit 5
+.equ	PB6,	6	;Port B Data Register bit 6
+.equ	PB7,	7	;Port B Data Register bit 7
+
+;DDRB
+.equ	DDB0,	0	;Port B Data Direction Register bit 0
+.equ	DDB1,	1	;Port B Data Direction Register bit 1
+.equ	DDB2,	2	;Port B Data Direction Register bit 2
+.equ	DDB3,	3	;Port B Data Direction Register bit 3
+.equ	DDB4,	4	;Port B Data Direction Register bit 4
+.equ	DDB5,	5	;Port B Data Direction Register bit 5
+.equ	DDB6,	6	;Port B Data Direction Register bit 6
+.equ	DDB7,	7	;Port B Data Direction Register bit 7
+
+;PINB
+.equ	PINB0,	0	;Port B Input Pins bit 0
+.equ	PINB1,	1	;Port B Input Pins bit 1
+.equ	PINB2,	2	;Port B Input Pins bit 2
+.equ	PINB3,	3	;Port B Input Pins bit 3
+.equ	PINB4,	4	;Port B Input Pins bit 4
+.equ	PINB5,	5	;Port B Input Pins bit 5
+.equ	PINB6,	6	;Port B Input Pins bit 6
+.equ	PINB7,	7	;Port B Input Pins bit 7
+
+
+;PORTC----------------------------------------------------------------
+
+;PORTC
+.equ	PC0,	0	;Port C Data Register bit 0
+.equ	PC1,	1	;Port C Data Register bit 1
+.equ	PC2,	2	;Port C Data Register bit 2
+.equ	PC3,	3	;Port C Data Register bit 3
+.equ	PC4,	4	;Port C Data Register bit 4
+.equ	PC5,	5	;Port C Data Register bit 5
+.equ	PC6,	6	;Port C Data Register bit 6
+
+;DDRC
+.equ	DDC0,	0	;Port C Data Direction Register bit 0
+.equ	DDC1,	1	;Port C Data Direction Register bit 1
+.equ	DDC2,	2	;Port C Data Direction Register bit 2
+.equ	DDC3,	3	;Port C Data Direction Register bit 3
+.equ	DDC4,	4	;Port C Data Direction Register bit 4
+.equ	DDC5,	5	;Port C Data Direction Register bit 5
+.equ	DDC6,	6	;Port C Data Direction Register bit 6
+
+;PINC
+.equ	PINC0,	0	;Port C Input Pins bit 0
+.equ	PINC1,	1	;Port C Input Pins bit 1
+.equ	PINC2,	2	;Port C Input Pins bit 2
+.equ	PINC3,	3	;Port C Input Pins bit 3
+.equ	PINC4,	4	;Port C Input Pins bit 4
+.equ	PINC5,	5	;Port C Input Pins bit 5
+.equ	PINC6,	6	;Port C Input Pins bit 6
+
+
+;PORTD----------------------------------------------------------------
+
+;PORTD
+.equ	PD0,	0	;Port D Data Register bit 0
+.equ	PD1,	1	;Port D Data Register bit 1
+.equ	PD2,	2	;Port D Data Register bit 2
+.equ	PD3,	3	;Port D Data Register bit 3
+.equ	PD4,	4	;Port D Data Register bit 4
+.equ	PD5,	5	;Port D Data Register bit 5
+.equ	PD6,	6	;Port D Data Register bit 6
+.equ	PD7,	7	;Port D Data Register bit 7
+
+;DDRD
+.equ	DDD0,	0	;Port D Data Direction Register bit 0
+.equ	DDD1,	1	;Port D Data Direction Register bit 1
+.equ	DDD2,	2	;Port D Data Direction Register bit 2
+.equ	DDD3,	3	;Port D Data Direction Register bit 3
+.equ	DDD4,	4	;Port D Data Direction Register bit 4
+.equ	DDD5,	5	;Port D Data Direction Register bit 5
+.equ	DDD6,	6	;Port D Data Direction Register bit 6
+.equ	DDD7,	7	;Port D Data Direction Register bit 7
+
+;PIND
+.equ	PIND0,	0	;Port D Input Pins bit 0
+.equ	PIND1,	1	;Port D Input Pins bit 1
+.equ	PIND2,	2	;Port D Input Pins bit 2
+.equ	PIND3,	3	;Port D Input Pins bit 3
+.equ	PIND4,	4	;Port D Input Pins bit 4
+.equ	PIND5,	5	;Port D Input Pins bit 5
+.equ	PIND6,	6	;Port D Input Pins bit 6
+.equ	PIND7,	7	;Port D Input Pins bit 7
+
+
+;External-Interrupts--------------------------------------------------
+
+;EICRA
+.equ	ISC00,	0	;External Interrupt Sense Control 0 Bit 0
+.equ	ISC01,	1	;External Interrupt Sense Control 0 Bit 1
+.equ	ISC10,	2	;External Interrupt Sense Control 1 Bit 0
+.equ	ISC11,	3	;External Interrupt Sense Control 1 Bit 1
+
+;EIMSK
+.equ	INT0,	0	;External Interrupt Request 0 Enable
+.equ	INT1,	1	;External Interrupt Request 1 Enable
+
+;PCICR
+.equ	PCIE0,	0	;Pin Change Interrupt Enable 0
+.equ	PCIE1,	1	;Pin Change Interrupt Enable 1
+.equ	PCIE2,	2	;Pin Change Interrupt Enable 2
+
+;PCMSK2
+.equ	PCINT16,0	;Pin Change Enable Mask 16
+.equ	PCINT17,1	;Pin Change Enable Mask 17
+.equ	PCINT18,2	;Pin Change Enable Mask 18
+.equ	PCINT19,3	;Pin Change Enable Mask 19
+.equ	PCINT20,4	;Pin Change Enable Mask 20
+.equ	PCINT21,5	;Pin Change Enable Mask 21
+.equ	PCINT22,6	;Pin Change Enable Mask 22
+.equ	PCINT23,7	;Pin Change Enable Mask 23
+
+;PCMSK1
+.equ	PCINT8,	0	;Pin Change Enable Mask 8
+.equ	PCINT9,	1	;Pin Change Enable Mask 9
+.equ	PCINT10,2	;Pin Change Enable Mask 10
+.equ	PCINT11,3	;Pin Change Enable Mask 11
+.equ	PCINT12,4	;Pin Change Enable Mask 12
+.equ	PCINT13,5	;Pin Change Enable Mask 13
+.equ	PCINT14,6	;Pin Change Enable Mask 14
+
+;PCMSK0
+.equ	PCINT0,	0	;Pin Change Enable Mask 0
+.equ	PCINT1,	1	;Pin Change Enable Mask 1
+.equ	PCINT2,	2	;Pin Change Enable Mask 2
+.equ	PCINT3,	3	;Pin Change Enable Mask 3
+.equ	PCINT4,	4	;Pin Change Enable Mask 4
+.equ	PCINT5,	5	;Pin Change Enable Mask 5
+.equ	PCINT6,	6	;Pin Change Enable Mask 6
+.equ	PCINT7,	7	;Pin Change Enable Mask 7
+
+;PCIFR
+.equ	PCIF0,	0	;Pin Change Interrupt Flag 0
+.equ	PCIF1,	1	;Pin Change Interrupt Flag 1
+.equ	PCIF2,	2	;Pin Change Interrupt Flag 2
+
+
+;SPI------------------------------------------------------------------
+
+;SPSR
+.equ	SPI2X,	0	;Double SPI Speed Bit
+.equ	WCOL,	6	;Write Collision Flag
+.equ	SPIF,	7	;SPI Interrupt Flag
+
+;SPCR
+.equ	SPR0,	0	;SPI Clock Rate Select 0
+.equ	SPR1,	1	;SPI Clock Rate Select 1
+.equ	CPHA,	2	;Clock Phase
+.equ	CPOL,	3	;Clock polarity
+.equ	MSTR,	4	;Master/Slave Select
+.equ	DORD,	5	;Data Order
+.equ	SPE,	6	;SPI Enable
+.equ	SPIE,	7	;SPI Interrupt Enable
+
+
+;Watchdog------------------------------------------------------------
+
+;WDTCSR
+.equ	WDP0,	0	;Watch Dog Timer Prescaler bit 0
+.equ	WDP1,	1	;Watch Dog Timer Prescaler bit 1
+.equ	WDP2,	2	;Watch Dog Timer Prescaler bit 2
+.equ	WDE,	3	;Watch Dog Enable
+.equ	WDCE,	4	;Watchdog Change Enable
+.equ	WDP3,	5	;Watchdog Timer Prescaler Bit 3
+.equ	WDIE,	6	;Watchdog Timeout Interrupt Enable
+.equ	WDIF,	7	;Watchdog Timeout Interrupt Flag
+
+
+;CPU-----------------------------------------------------------------
+
+;SREG
+.equ	SREG_C,	0	;Carry Flag
+.equ	SREG_Z,	1	;Zero Flag
+.equ	SREG_N,	2	;Negative Flag
+.equ	SREG_V,	3	;Two's Complement Overflow Flag
+.equ	SREG_S,	4	;Sign Bit
+.equ	SREG_H,	5	;Half Carry Flag
+.equ	SREG_T,	6	;Bit Copy Storage
+.equ	SREG_I,	7	;Global Interrupt Enable
+
+;CLKPR
+.equ	CLKPS0,	0	;Clock Prescaler Select Bit 0
+.equ	CLKPS1,	1	;Clock Prescaler Select Bit 1
+.equ	CLKPS2,	2	;Clock Prescaler Select Bit 2
+.equ	CLKPS3,	3	;Clock Prescaler Select Bit 3
+.equ	CLKPCE,	7	;Clock Prescaler Change Enable
+
+;SPMCSR
+.equ	SELFPRG,0	;Self Programming Enable
+.equ	PGERS,	1	;Page Erase
+.equ	PGWRT,	2	;Page Write
+.equ	BLBSET,	3	;Boot Lock Bit Set
+.equ	RWWSRE,	4	;Read-While-Write section read enable
+.equ	RWWSB,	6	;Read-While-Write Section Busy
+.equ	SPMIE,	7	;SPM Interrupt Enable
+
+;MCUCR
+.equ	PUD,	4	;Pull-up Disable 
+.equ	BODSE,	5	;BOD Sleep Enable
+.equ	BODS,	6	;BOD Sleep
+
+;MCUSR
+.equ	PORF,	0	;Power-on reset flag
+.equ	EXTRF,	1	;External Reset Flag
+.equ	BORF,	2	;Brown-out Reset Flag
+.equ	WDRF,	3	;Watchdog Reset Flag
+
+;SMCR
+.equ	SE,	0	;Sleep Enable
+.equ	SM0,	1	;Sleep Mode Select Bit 0
+.equ	SM1,	2	;Sleep Mode Select Bit 1
+.equ	SM2,	3	;Sleep Mode Select Bit 2
+
+;PRR
+.equ	PRADC,	0	;Power Reduction ADC
+.equ	PRUSART,1	;Power Reduction USART
+.equ	PRSPI,	2	;Power Reduction Serial Peripheral Interface
+.equ	PRTIM1,	3	;Power Reduction Timer/Counter1
+.equ	PRTIM0, 5	;Power Reduction Timer/Counter0
+.equ	PRTIM2,	6	;Power Reduction Timer/Counter2
+.equ	PRTWI,	7	;Power Reduction TWI
+
+
+;EEPROM---------------------------------------------------------------
+
+;EECR
+.equ	EERE,	0	;EEPROM Read Enable
+.equ	EEPE,	1	;EEPROM Write Enable
+.equ	EEMPE,	2	;EEPROM Master Write Enable
+.equ	EERIE,	3	;EEPROM Ready Interrupt Enable
+.equ	EEPM0,	4	;EEPROM Programming Mode Bit 0
+.equ	EEPM1,	5	;EEPROM Programming Mode Bit 1
+
+
+;LOCK-Bits------------------------------------------------------------
+
+.equ	LB1,	0	;Lock bit
+.equ	LB2,	1	;Lock bit
+.equ	BLB01,	2	;Boot Lock bit
+.equ	BLB02,	3	;Boot Lock bit
+.equ	BLB11,	4	;Boot lock bit
+.equ	BLB12,	5	;Boot lock bit
+
+
+;FUSES----------------------------------------------------------------
+
+;LOW
+.equ	CKSEL0,	0	;Select Clock Source
+.equ	CKSEL1,	1	;Select Clock Source
+.equ	CKSEL2,	2	;Select Clock Source
+.equ	CKSEL3,	3	;Select Clock Source
+.equ	SUT0,	4	;Select start-up time
+.equ	SUT1,	5	;Select start-up time
+.equ	CKOUT,	6	;Clock output
+.equ	CKDIV8,	7	;Divide clock by 8
+
+;HIGH
+.equ	BOOTRST,0	;Select reset vector
+.equ	BOOTSZ0,1	;Select boot size
+.equ	BOOTSZ1,2	;Select boot size
+.equ	EESAVE,	3	;EEPROM memory is preserved through chip erase
+.equ	WDTON,	4	;Watchdog Timer Always On
+.equ	SPIEN,	5	;Enable Serial programming and Data Downloading
+.equ	DWEN,	6	;debugWIRE Enable
+.equ	RSTDIS, 7	;External reset disable
+
+;EXTENDED
+.equ	BODLVL0,0	;Brown-out Detector trigger level
+.equ	BODLVL1,1	;Brown-out Detector trigger level
+.equ	BODLVL2,2	;Brown-out Detector trigger level
+
+
+;DATA-Section---------------------------------------------------------
+
+.equ	FLASHEND,  0x3fff	
+.equ	IOEND,     0x00ff
+.equ	SRAM_START,0x0100
+.equ	SRAM_SIZE, 2048
+.equ	RAMEND,	   0x08ff
+.equ	XRAMEND,   0x0000
+.equ	E2END,	   0x03ff
+.equ	EEPROMEND, 0x03ff
+.equ	EEADRBITS, 10
+
+
+;Bootloader-----------------------------------------------------------
+
+.equ	NRWW_START_ADDR,	0x3800
+.equ	NRWW_STOP_ADDR,		0x3fff
+.equ	RWW_START_ADDR,		0x0
+.equ	RWW_STOP_ADDR,		0x37ff
+.equ	PAGESIZE,	64
+.equ	FIRSTBOOTSTART,		0x3f00
+.equ	SECONDBOOTSTART,	0x3e00
+.equ	THIRDBOOTSTART,		0x3c00
+.equ	FOURTHBOOTSTART,	0x3800
+.equ	SMALLBOOTSTART,		FIRSTBOOTSTART
+.equ	LARGEBOOTSTART,		FOURTHBOOTSTART
+

Source/ASM_Source/global.inc

@@ -0,0 +1,51 @@
+;Register---------------------------------------------------------------
+
+.equ	main_r,			16
+.equ	usart_r,		17
+.equ	spi_r,			18
+.equ	timer1_r,		19
+
+
+.equ	frame,			21
+.equ	mode,			22
+.equ	option,			23
+.equ	true,			24
+.equ	false,			25
+
+.equ	X_l,			26
+.equ	X_h,			27
+.equ	Y_l, 			28
+.equ	Y_h,			29
+.equ	Z_l,			30
+.equ	Z_h,			31	
+
+
+;Konstanten-------------------------------------------------------------
+
+.equ	fuse_read,		0 							;Program-Mode		
+.equ	fuse_write,		1
+.equ	page_read,		2
+.equ 	page_write,		3
+.equ	prog_read,		4
+
+.equ	Baud,			0x0033						;USART-Baudr. 19.2k
+
+.equ	cmd_ptr,		0x0100						;Pointer
+.equ	page_ptr,		0x0200						
+
+;Bitmasken--------------------------------------------------------------
+
+.equ	nibble_lo,		0x0F
+.equ	nibble_hi,		0xF0
+.equ	frame_mask,		0x90
+
+;Variablen--------------------------------------------------------------
+
+.equ	cmd_mode,		0x0100
+.equ	cmd_opt_lo,		0x0101
+.equ	cmd_opt_hi,		0x0102	
+
+
+.equ	timer1_cnt,		0x0110
+.equ	timer1_bool,	0x0111
+.equ	timer1_MAX,		0x0112

Source/ASM_Source/linker.ld

@@ -0,0 +1,18 @@
+MEMORY {
+	FLASH	: ORIGIN = 0x0000, LENGTH = 16384
+	SRAM	: ORIGIN = 0x800100, LENGTH = 2048
+	EEPROM	: ORIGIN = 0X810000, LENGTH = 1024
+}
+
+SECTIONS {
+	.text	: {
+		*(.vec);
+		*(.text);
+	} >FLASH
+	.data	: {
+		*(.data);
+	} >SRAM
+	.eeprom : {
+		*(.eeprom);
+	} >EEPROM
+}

Source/ASM_Source/main.s

@@ -0,0 +1,115 @@
+;Incs and Defs---------------------------------------------------------
+
+.include "atm328p.inc"
+.include "global.inc"
+
+;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+;Main Programm
+
+.global main
+main:
+	ldi		main_r, lo8(RAMEND)						;Stackpointer
+	out		SPL, main_r
+	ldi		main_r, hi8(RAMEND)
+	out		SPH, main_r
+
+	clr		false									;set Registers
+	ser		true
+
+	call	usart_init;								;init USART
+
+	ldi		main_r, (1<<PC0)|(1<<PC1)|(1<<PC2)|(1<<PC3)|(1<<PC4)	
+	out		DDRC, main_r							;init I/O
+	out 	PORTC, false
+
+	sei												;enable Interrupts
+
+	rjmp	mode_select								;select Mode
+	rjmp	.-2										;Endlosschleife
+	cli												;disable Interrupts
+
+;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+;Mode Selection
+
+mode_select:
+
+sbi		PORTC, PC0				;delete
+
+;Receive Frame----------------------------------------------------------
+	ldi		X_l, lo8(cmd_ptr)						;set Command-Ptr
+	ldi		X_h, hi8(cmd_ptr)
+	lds		usart_r, UCSR0B							;activate Receiver
+	sbr 	usart_r, (1<<RXEN0)|(1<<RXCIE0)
+	sts		UCSR0B, usart_r
+
+	cpi		X_l, 0x03								;check if Frame rec
+	brne	.-4
+
+	lds		usart_r, UCSR0B							;disable Receiver
+	cbr 	usart_r, (1<<RXEN0)|(1<<RXCIE0)
+	sts		UCSR0B, usart_r
+	sts		UDR0, false								;clear UDR
+
+sbi		PORTC, PC1				;delete
+
+	call	cmd_rebuild								;read Cmd
+
+;Select Mode------------------------------------------------------------
+;	lds		mode, cmd_mode 
+;	sbrc  	mode, fuse_read
+;	rjmp	mode_select
+;	sbrc  	mode, fuse_write
+;	rjmp	mode_select
+;	sbrc  	mode, page_read
+;	rjmp	mode_select
+;	sbrc	mode, page_write
+;	rjmp	mode_select
+;	sbrc  	mode, prog_read
+;	rjmp	mode_select
+
+;Send Frame-------------------------------------------------------------
+
+	ldi		X_l, lo8(cmd_ptr)						;set Command-Ptr
+	ldi		X_h, hi8(cmd_ptr)
+	lds		usart_r, UCSR0B							;enable UDRI
+	sbr 	usart_r, 1<<UDRIE0
+	sts		UCSR0B, usart_r
+	cpi		X_l, 0x03								;check if Frame send
+	brne	.-4
+	lds		usart_r, UCSR0B							;disable TX, TXCI
+	cbr 	usart_r, (1<<TXEN0)|(1<<TXCIE0)|(1<<UDRIE0)		
+	sts		UCSR0B, usart_r
+	sts		UDR0, false								;clear UDR
+
+sbi		PORTC, PC2				;delete
+
+	rjmp 	mode_select
+
+;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+;Cmd rebuild
+
+cmd_rebuild:
+	lds 	main_r, cmd_mode						;set Mode
+	andi	main_r, nibble_lo
+	ldi		mode, 0x01
+	tst		main_r									
+	breq	.+6
+	lsl		main_r
+	dec 	main_r
+	rjmp	.-8
+	clr 	option									;set Option
+	lds		main_r, cmd_opt_lo
+	andi	main_r, nibble_lo
+	or		option, main_r
+	lds		main_r, cmd_opt_hi
+	andi	main_r, nibble_lo
+	swap	main_r
+	or		option, main_r
+
+	sbi		PORTC, PC1				;delete
+
+	ret
+
+
+
+

Source/ASM_Source/makefile

@@ -0,0 +1,35 @@
+#Commands and Variables-------------------------------------------------
+as = avr-as -mmcu=avr5
+ld = avr-ld
+objs = main.o vectab.o usart.o timer1.o
+
+#Settings---------------------------------------------------------------
+.SILENT	:
+
+#Operations-------------------------------------------------------------
+.PHONY	: all
+all		: prog.hex clean
+
+#generating HEX---------------------------------------------------------
+prog.hex: prog.o
+	avr-objcopy prog.o -O ihex prog.hex
+	echo Build complete!
+
+#linking Objects--------------------------------------------------------
+prog.o 	: $(objs) 
+	$(ld) $(objs) -o prog.o -T linker.ld
+
+#assembling files-------------------------------------------------------
+main.o	: main.s 
+	$(as) main.s -o main.o
+vectab.o: vectab.s
+	$(as) vectab.s -o vectab.o
+usart.o : usart.s
+	$(as) usart.s -o usart.o
+timer1.o: timer1.s
+	$(as) timer1.s -o timer1.o
+
+#clear directory--------------------------------------------------------
+.PHONY	: clean
+clean	:
+	rm $(objs)

Source/ASM_Source/prog.hex

@@ -0,0 +1,27 @@
+:100000000C9434000C9400000C9400000C9400003C
+:100010000C9400000C9400000C9400000C94000060
+:100020000C9400000C9400000C9400000C94000050
+:100030000C9400000C94C0000C9400000C94000080
+:100040000C9400000C9400000C9490000C949A0006
+:100050000C94A6000C9400000C9400000C9400007A
+:100060000C9400000C9400000FEF0DBF08E00EBFD1
+:1000700099278FEF0E947E000FE107B998B9789415
+:1000800002C0FFCFF894409AA0E0B1E01091C10007
+:1000900010691093C100A330F1F71091C1001F76D1
+:1000A0001093C1009093C600419A0E946900A0E09D
+:1000B000B1E01091C10010621093C100A330F1F7BC
+:1000C0001091C10017791093C1009093C600429A15
+:1000D000DACF009100010F7061E0002319F0000FEA
+:1000E0000A95FCCF7727009101010F70702B0091CA
+:1000F00002010F700295702B419A08959093C600EB
+:100100009093C0009093C1009093C20010E01093B0
+:10011000C50013E31093C40016E01093C2000895C5
+:100120001F935091C600152F107F103909F45D936D
+:100130001F9118951F935D915093C6001091C100B7
+:100140001F7D18641093C1001F9118951F93109183
+:10015000C100177B10621093C1001F9118959093F6
+:1001600080009093810090938200909385009093FB
+:10017000840090936F009093100190931101089563
+:100180003F9330911001339520911201321719F4E9
+:0E019000332780931101309310013F91189591
+:00000001FF

Source/ASM_Source/timer1.s

@@ -0,0 +1,37 @@
+;Incs and Defs----------------------------------------------------------
+
+.include "atm328p.inc"
+.include "global.inc"
+
+;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+;Timer-Reset
+
+.global timer1_reset
+timer1_reset:
+	sts		TCCR1A, false						;clear Registers
+	sts		TCCR1B, false
+	sts		TCCR1C, false
+	sts		TCNT1H, false
+	sts		TCNT1L, false
+	sts		TIMSK1, false
+	sts		timer1_cnt, false					;set Variables
+	sts		timer1_bool, false
+	ret
+
+
+;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+;Overflow-Interrupt
+
+.global timer1_OVF
+timer1_OVF:
+	push	timer1_r
+	lds		timer1_r, timer1_cnt				;Timer-Scaling
+	inc 	timer1_r
+	lds		spi_r, timer1_MAX							
+	cp		timer1_r, spi_r
+	brne	.+6
+	clr		timer1_r							;timed instructions
+	sts		timer1_bool, true
+	sts		timer1_cnt, timer1_r
+	pop		timer1_r
+	reti

Source/ASM_Source/usart.s

@@ -0,0 +1,64 @@
+;Incs and Defs---------------------------------------------------------
+
+.include "atm328p.inc"
+.include "global.inc"
+
+;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+;USART-Initialize
+
+.global usart_init
+usart_init:
+	sts		UDR0, false								;clear Registers
+	sts		UCSR0A, false
+	sts		UCSR0B, false
+	sts		UCSR0C, false
+	ldi		usart_r, hi8(Baud)						;set Baudrate
+	sts		UBRR0H, usart_r							;to 19.2k
+	ldi		usart_r, lo8(Baud)
+	sts		UBRR0L, usart_r
+	ldi		usart_r, (1<<UCSZ01)|(1<<UCSZ00)		;8-Bit Character
+	sts		UCSR0C, usart_r 						;Aysnchonous USART
+	ret
+
+;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+;RXC-Interrupt-Handler
+
+.global usart_RXC
+usart_RXC:
+	push	usart_r
+	lds		frame, UDR0								;read Frame
+	mov		usart_r, frame
+	andi	usart_r, nibble_hi						;check Frame
+	cpi		usart_r, frame_mask
+	brne	.+2
+	st 		X+, frame 								;store Frame
+	pop		usart_r
+	reti
+
+;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+;UDRE-Interrupt-Handler
+
+.global usart_UDRE
+usart_UDRE:
+	push	usart_r
+	ld 		frame, X+ 								;load new Frame
+	sts		UDR0, frame								;set Frame
+	lds		usart_r, UCSR0B
+	cbr		usart_r, 1<<UDRIE0 						;disable UDREI
+	sbr 	usart_r, (1<<TXEN0)|(1<<TXCIE0)			;enable TX, TXCI
+	sts 	UCSR0B, usart_r
+	pop		usart_r
+	reti
+			
+;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+;TXC-Interrupt-Handler
+
+.global usart_TXC
+usart_TXC:
+	push	usart_r
+	lds		usart_r, UCSR0B
+	cbr 	usart_r, (1<<TXEN0)|(1<<TXCIE0)			;disable TX, TXCI
+	sbr		usart_r, 1<<UDRIE0 						;enable UDREI
+	sts 	UCSR0B, usart_r
+	pop		usart_r
+	reti

Source/ASM_Source/vectab.s

@@ -0,0 +1,38 @@
+;Deklaration von Interrupt-Handlern-------------------------------------
+
+.global main
+.global timer1_OVF
+.global usart_RXC
+.global	usart_UDRE
+.global usart_TXC
+
+;Vektortabelle----------------------------------------------------------
+
+.section .vec
+reset:	jmp		main			;Reset-Handler
+		jmp		reset			;INT0-Handler
+		jmp		reset			;INT1-Handler
+		jmp		reset			;PCINT0-Handler
+		jmp		reset			;PCINT1-Handler
+		jmp		reset			;PCINT2-Handler
+		jmp		reset			;WDog-Handler
+		jmp		reset			;TMR2_CMPA-Handler
+		jmp		reset			;TMR2_CMPB-Handler
+		jmp		reset 			;TMR2_OVF-Handler
+		jmp		reset			;TMR1_CAPT-Handler
+        jmp     reset       	;TMR1_CMPA-Handler
+        jmp     reset       	;TMR1_CMPB-Handler
+        jmp     timer1_OVF 	 	;TMR1_OVF-Handler
+        jmp     reset       	;TMR0_CMPA-Handler
+        jmp     reset       	;TMR0_CMPB-Handler
+        jmp     reset			;TMR0_OVF-Handler
+		jmp		reset			;SPI_Transfer complete
+		jmp		usart_RXC		;USART_Rx complete
+		jmp 	usart_UDRE		;USART_Register empty
+		jmp 	usart_TXC		;USART_Tx complete
+		jmp 	reset			;ADC_Conversion complete
+		jmp 	reset			;EEPROM_Ready
+		jmp		reset			;Analog comparator
+		jmp 	reset			;TWI_Interface
+		jmp		reset			;SPM_Ready
+